Gate dopant penetration and lateral diffusion in a multi-layered dual-doped polysilicon structure adversely affects the fabrication yield and the performance of integrated circuits constructed from such structures. To prevent gate dopant penetration during formation of n+ and p+ polysilicon gates, two photoresist masks are typically applied and removed at different stages of the fabrication process which, of course, increases the expense of the fabrication process. While the thermal budget (i.e., the temperature and time fabrication parameters) may be reduced to limit the amount of dopant penetration, reducing lateral diffusion of gate dopants during subsequent processing steps, i.e., steps performed after the n+ and p+ polysilicon gates have been formed, presents a more vexing problem. Although some Boron diffusion may be acceptable, it is desirable to minimize the amount so that the performance of the semiconductor device manufactured from the structure is not adversely effected (i.e., too much Boron diffusion will change the characteristics of the n+ type polysilicon and hence the NMOS device (transistor)). Here too the thermal budget may be reduced to address gate dopant diffusion. In addition, Tungsten-Silicide or Tungsten alone may be eliminated from the structure. However, this results in a high gate sheet resistance.
There thus exists a need in the art for a method of fabricating a multi-layered dual-doped polysilicon structure that overcomes the above-described shortcomings of the prior art.